The implementation of complex signal processing functionality on an integrated circuit requires a variety of circuit elements, such as transistors, resistors, and capacitors. Some integrated circuit fabrication processes provide a "precision" capacitor for uses including switched-capacitor filters, digital-to-analog converters (DACs), and analog-to-digital converters (ADCs), such as in telecommunications, implantable medical devices, and other applications.
One integrated circuit capacitor includes separately formed conductive polysilicon layers having an insulator interposed therebetween. The first-formed polysilicon layer is referred to as the bottom plate of the capacitor, and the second-formed polysilicon layer is referred to as the top plate of the capacitor. The bottom plate is formed over the integrated circuit semiconductor substrate, and is separated therefrom by an insulator. Connection is made to each of the bottom and top plates by contact and metal layers. A protective passivation layer is formed over the top plate of the capacitor and the entire integrated circuit.
The above-described capacitor structure includes an unwanted parasitic capacitor, consisting of the bottom plate and substrate as parasitic capacitor terminals, and the insulator between the bottom plate and substrate as a parasitic capacitor dielectric. The unwanted parasitic capacitor, which is referred to as the bottom plate parasitic capacitor, can have a capacitance value that is approximately 10% of the capacitance value of the desired capacitor. As a result, designers of switched-capacitor integrated circuits adopt circuit designs that are insensitive to the bottom plate parasitic capacitor.
The above-described capacitor structure also includes a second unwanted parasitic capacitor, consisting of the top plate as a first parasitic capacitor terminal and at least one other circuit node, such as the substrate, as a second parasitic capacitor terminal. Passivation and other insulating layers form a second parasitic capacitor dielectric. The second unwanted parasitic capacitor, which is referred to as a top plate parasitic capacitor, results from electric fields originating from the top plate, passing through the superjacent dielectric passivation layer and the air above the passivation layer, and terminating at the substrate or other circuit nodes. Although the dielectric passivation layer can have a significant premittivity, the air above the passivation layer has a low permittivity. As a result, the top plate parasitic capacitor typically has a capacitance value that is relatively small, and circuit designs may be relatively unaffected by the top plate parasitic capacitor.
However, manufacturers of electronic devices using integrated circuits often require an additional coating over the passivation layer of the integrated circuit die. Such die coatings provide encapsulation of the integrated circuit die, resulting in numerous practical advantages. For example, a die coating may provide opacity so that the underlying semiconductor integrated circuit is unaffected by incident light, such as during testing of the integrated circuit or otherwise. In another example, the die coating may be used to adhere other electronic components of an electronic system to the integrated circuit die.
Unfortunately, the materials used for integrated circuit die coatings (e.g., epoxy, polyamide, etc.) often have a large permittivity, thereby increasing the value of the unwanted top plate parasitic capacitor. These die coatings are relatively thick and replace the low-permittivity air space above the die. As a result, the electric fields of the top plate parasitic capacitor pass through the superjacent dielectric passivation layer and the die coating above the passivation layer. Since both the passivation layer and die coating have a high permittivity, the capacitance value of the unwanted top plate parasitic capacitor increases, resulting in deleterious effects on circuit operation.
For example, the increased top plate parasitic capacitance can introduce nonlinearity in a digital-to-analog converter. Furthermore, since the die coating process may not be well-controlled, the die coating thickness may vary between capacitors on the same integrated circuit die as well as between different integrated circuit die. Such variations in die coating thickness introduce variations in top plate parasitic capacitance values. The increased top plate parasitic capacitance values and variations thereof are difficult to correct for using traditional digital-to-analog converter calibration and compensation techniques.
For these reasons, and other reasons that will become apparent upon reading the following detailed description of the invention, there is a need for providing an integrated circuit capacitor that is insensitive to parasitic capacitances, particularly those parasitic capacitors introduced by overlying dielectric layers. There is also a need for reducing the integrated circuit die area of the capacitor. There is a further need for improving the operation of digital-to-analog converters, analog-to-digital converters, switched-capacitor filters, and other signal processing circuits, by reducing the sensitivity of such circuits to parasitic capacitances, signal crosstalk, and external noise.